ParaFPGA2015: Parallel Computing with FPGAs

Dirk Stroobandt, Erik D'Hollander (Ghent University), Abdellah Touhafi (Brussels University)

Contact: parafpga at elis.ugent.be Website: parafpga2015.elis.ugent.be

Programhttp://parafpga2015.elis.ugent.be/program.html

ParaFPGA focuses on parallel techniques for using FPGAs as accelerator in high performance computing areas such as supercomputing, embedded systems and big data computing.

Field Programmable Gate Arrays emerge as powerful building blocks for High Performance Systems. The freedom to build tailored architectures with extremely low power is one of the key milestones on the path to exascale computing. Recently the major industrial players invested heavily in high-level synthesis tools and established well known programming paradigms to facilitate the march towards programmable hardware. In addition, the famous memory wall has been alleviated by incorporating processing cores inside the FPGA fabric.

Of special interest are design methods, heterogeneous architectures and algorithms optimized for execution on FPGAs. Design methods include optimizing the resource utilization, development time and high-level synthesis tools. Heterogeneous architectures encompass multi-FPGAs, FPGAs with CPU cores and systems combining FPGAs, GPUs and CPUs. Algorithms ready-made for FPGAs range from streaming applications to fast dynamic reconfiguration and feature a substantial performance increase.

Researchers and practitioners are invited to submit novel contributions in the areas of high-level synthesis, dynamic reconfiguration and high performance applications. Papers are invited on a wide variety of topics related but not limited to:

  • high-level synthesis techniques and case studies
  • optimizing throughput of streaming applications
  • non-uniform memory partitioning and data reuse
  • dataflow engines for irregular applications
  • heterogeneous on-chip processor and programmable logic codesign
  • evaluating performance metrics for high-level synthesis
  • scalability of multi-core with multi-FPGA architectures
  • OpenCL for FPGA applications
  • high-level synthesis guided design space exploration
  • high-level partial and dynamic reconfiguration
  • performance-driven resource and area optimization

Submission deadline: June 1, 2015

Notification of acceptance: July 15, 2015

Date of Mini Symposium: September 1, 2015

Submissions: https://www.easychair.org/conferences/?conf=parafpga2015

Last updated: 14 Aug 2015 at 15:05