Symposium on High Level Languages for Parallel Computing on FPGAs

Rob Stewart, Deepayan Bhowmik, Greg Michaelson (Heriot-Watt University)

Contact: R [dot] stewart [at] hw [dot] ac [dot] uk (subject: Parco%202015%20MIni%20Symposium) (R.Stewart at hw.ac.uk)  Website: www.macs.hw.ac.uk/~rs46/parco15-high-level-fpga-languages

The key advantage of FPGAs is the ability to configure logic gates to meet very specific application requirements, for highly efficient program acceleration exploiting the fine-grained parallel nature of FPGAs. FPGAs are most commonly programmed with hardware description languages (HDL) and intellectual property (IP) cores directly. At this low level, identifying opportunities for coarse-grained program optimisation and increased parallelism is difficult. Alternative approaches abstract to higher level program specification, with compilers that generate HDL from standard C, dataflow with explicit wiring, DSLs for circuit design and recently OpenCL kernels. The high level language design challenge is to trade-off language expressivity with efficient synthesis, and to introduce language constructs that FPGA compilers can exploit with performance optimisation's.

This mini-symposia brings together language designers and compiler engineers. Researchers from academia and industry are invited to submit novel contributions on a variety of topics related but not limited to:

  • language constructs, abstractions & extensions for FPGAs.
  • domain specific languages for parallel computation on FPGAs.
  • FPGA compiler techniques that trade-off parallelism, FPGA area, throughput, scalability, power use & communication costs.

Submission deadline: June 22, 2015

Notification of acceptance: July 27, 2015

Mini Symposium: September 2, 2015 Canceled

Submissions: https://easychair.org/conferences/?conf=hlfpga2015

Last updated: 14 Aug 2015 at 14:32